An Area Efficient Readout Curcuit for CMOS Image Sensor with Lateral Overflow Integration Capacitor

2022 Dec.

Authors Ai Otani*, Hiroaki Ogawa*, Ken Miyauchi, Sangman Han, Hideki Owada, Isao Takayanagi and Shunsuke Okura*
*Ritsumeikan University

5th International Workshop on Image Sensors and Imaging SystemsWorkshop (IWISS2022)

A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can realize high dynamic range (HDR) imaging with low conversion gain (LCG) signal for large full well capacity and with high conversion gain (HCG) signal for small dark noise. However, the LOFIC CIS requires 2-channel readout circuits channel readout circuits for LCG and HCG signals whose signal polarities are inverted. In order to provide cost efficient LOFIC CIS, a 1-channle readout circuit which can process both HCG and LCG signals is presented in this paper. The combination circuit of an inverting amplifier for HCG signal and a non-inverting attenuator for LCG signal can reduce the area of the readout circuit by half compared to the conventional 2-channel readout circuit. The readout circuit is fabricated with a 0.18um CMOS process with MIM capacitor, achieving the readout noise of 130uVrms in the HCG mode and the signal range 1.3V in the LCG mode.