Paper
Evolution of digital pixel sensor (DPS) and advancement by stacking technologies
2024 Oct
IEEE SENSORS 2024
https://2024.ieee-sensorsconference.org/
This presentation reviews the evolution of digital pixel sensor (DPS) and its increasing benefits by the advancement of chip-stacking technologies to integrate in-pixel ADC circuit in standard logic process with photo diode (PD) in CIS specific process. Further increase of the stacked-chip count enables more integration of such on-sensor processing circuit for image-signal processing (ISP) and computer vision (CV) applications. Recent publications on Brillnics DPS products which feature high dynamic range (HDR) voltage mode global shutter (VMGS) by a unique triple-quantization (3Q) ADC scheme are introduced. An example of embedded-circuit integration by three-layer stacking technology in Brillnics is also dicussed to focus on the on-chip image processing for sensor performance improvement by pixel-wise fixed-pattern noise (FPN) correction. Finally, the future perspectives of the advancement of on-sensor processor for edge-computing applications is discussed.