Paper

A 400×400 3.24μm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor

2025 Feb

Authors Tsung-Hsun Tsai, Kwuang-Han Chang, Andrew Berkovich, Raffaele Capoccia, Song Chen, Zhao Wang, Chiao Liu, Yi-Hsuan Lin, Sheng-Yeh Lai, Hao-Ming Hsu, Hirofumi Abe, Kazuya Mori, Hideyuki Fukuhara, Chih-Hao Lin, Toshiyuki Isozaki, Wei-Chen Li, Wei-Fan Chou, Masayuki Uno, Rimon Ikeno, Masato Nagamatsu, Guang Yang, Shou-Gwo Wuu, Lyle Bainbridge

IEEE International Solid-State Circuits Conference (ISSCC)
https://ieeexplore.ieee.org/document/10904717

In recent years, digital pixel sensors (DPS) have been developed for augmented reality (AR) glasses and virtual reality (VR) headsets. Thanks to a 2-layer stacked process, DPS provides low power consumption, high dynamic range (HDR) and global shutter in a small pixel size [1], [2]. To meet the increasingly important form factor and performance requirements of these devices, a 3-layer stacked DPS with a 3.24∪m pixel is developed to reduce the chip size while incorporating a frame averaging unit (FAU), image signal processing (ISP), and sparse transmission (ST) functionalities. The 3.24μm pixel is achieved with a single-ended comparator, optimized control logic and a 10b in-pixel SRAM memory to offer single-exposure HDR capture. The sensor significantly improves noise performance by correcting the fixed-pattern noise (FPN) with FAU and ISP, and ST enables various artificial intelligence (AI) and computer vision (CV) use cases with a low power consumption. The sensor has a die size of 2.47×1.85mm2, suitable for AR and VR devices where small cameras are demanded.