High-Speed, Low-Noise Sensor Architecture

Our CMOS image sensor technology adopts a column-parallel signal processing architecture for high-speed, low-noise signal readout. This architecture has been used for various high-speed (or high-frame rate) CMOS image sensors. The required signal processing speed for a given frame rate is much lower than “serial” signal processing architecture, where the analog-to-digital conversion is performed by a chip-level ADC. With our technology, a number of signal chains operate in parallel, which in turn results in higher signal fidelity, lower noise and lower power consumption.

Possible column-wise FPN that could appear due to performance variations in the column-parallel signal chain has been successfully suppressed by Brillnics’ design techniques.