Backside Illuminated High Dynamic Range 3.0um Pixel Featuring Vertical p-n Junction Capacitance in a Deep Pinned Photodiode

2017 May30 – Jun2

Authors K. Mori, S. Okura, T. Hasegawa, S. Tanaka and I. Takayanagi

2017 International Image Sensor Workshop (IISW)

High linear full well capacity (LFWC) is required to obtain high-fidelity high dynamic range performance in a single exposure high dynamic range (SEHDR1)) scheme in the CMOS image sensor. However, due to the deep pinned photo diode structure2) that is commonly used for back side illuminated devices, LFWC does not increase in proportion to the pixel size, since the pinning voltage increases as pixel size increases, while the supply voltage needs to be kept. In this paper, a high LFWC for 3.0μm pixel, which is relatively a large pixel in recent commercial BSI devices, using a latest 65nm BSI pixel process technology, is presented as a pixel for a 1/2.7”, 2M-pixel CMOS image sensor1). To increase the LFWC of the 3.0m pixel, vertical p-n junction capacitance in the pinned photodiode is utilized. The developed pixel shows high performance, such as 77% peak QE, LFWC of 40ke-, blooming and image lag free, and average dark current of less than 25e-/s/pixel at 60°C.