Paper
Low-noise reset transistor for LOFIC CMOS image sensors using a two-step reset scheme
2025 November
The 2025 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)
https://www.ieee-jp.org/section/kansai/chapter/eds/imfedk/
A CMOS image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) enables high dynamic range (HDR) imaging by combining low-noise signal with high full-well capacity (FWC) signal. However, the signal-to-noise ratio (SNR) degrades at the switching point due to kTC noise generated during the pixel reset operation for the high-FWC signal. To mitigate this issue, we have proposed a two-step reset (TSR) scheme for LOFIC CIS that incorporates an additional reset switch and external capacitor outside the pixel array to suppress the reset noise. In this work, we further enhance noise sup pression by introducing an asymmetric in-pixel reset transistor. Three reset transistors are presented and implemented in a prototype CIS fabricated using a 0.18 µm CMOS process. The measurement results show that the pixel reset noise is reduced to 0.87 mVrms, corresponding to a 60.1 % reduction compared with a conventional LOFIC pixel.