Paper
An Area-Efficient and Low-Power Single-Slope A/D Converter Merged with a Pixel Transistor for CMOS Image Sensors
2025 July
The International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)
https://www.itc-cscc2025.org/2025/
Toward the ”Trillion Sensors Universe,” we propose a single-slope (SS) A/D converter (ADC) that utilizes a pixel transistor as part of the ADC, to achieve a small-area and low-power readout circuit for CMOS image sensors (CIS). In order to further reduce power consumption, a dynamically controlled ramp buffer is also presented. According to SPICE simulation results, the proposed SS-ADC respectively reduces power consumption and input-referred noise by 41.0% and 11.2%, compared to conventional readout circuits using the pixel source follower (SF). Furthermore, the ramp buffer achieved a 78.5% reduction in average power consumption by dynamically adjusting driving capability for the SS-ADC. Layout results also demonstrates that the circuit area is reduced by 30.0% compared to conventional readout circuit.