Brillnics presented 3 papers at the 2017 IISW
Brillnics presented 3 papers at the 2017 International Image Sensor Workshop (IISW) that was held from May 30th till June 2nd in Hiroshima, Japan.
The first paper, “An 87dB Single Exposure Dynamic Range CMOS Image Sensor with a 3.0mm Triple Conversion Gain Pixel”, by Isao Takayanagi, et al., reports sensor architecture and performance of a 2M-pixel CMOS image sensor (BR0200) that features 87dB single exposure high dynamic range (SE HDR). With the SE HDR scheme, the motion artifact with moving objects that could appear in the multiple exposure HDR (ME HDR) scheme cannot be generated. Also, the advantage of offering higher SNR at high light levels over the ME HDR scheme was pointed out.
The second paper, “Back Side Illuminated High Dynamic Range 3.0μm Pixel Featuring Vertical p-n Junction Capacitance in A Deep Pinned Photodiode,” by K. Mori, et al., describes the pixel structure that can enhance photodiode full well capacity (FWC). This pixel structure is used for BR0200. With this pixel structure, 40ke- FWC has been obtained, though a pixel that yields 27ke- FWC for a balanced pixel performance is chosen for BR0200.
The third paper, “A Proposal of PUF Utilizing Pixel Variations in a CMOS Image Sensor,” by S. Okura, et al., proposes a CMOS image sensor with a physically unclonable function (CIS-PUF) in collaboration with Ritsumeikan University, Kyoto, Japan, which utilizes the pixel-to-pixel fixed pattern noise (PPFPN) as a fingerprint of each device. It is expected that this PUF scheme will contribute to information security that will be required in future IoT environment.
Those papers can be found in the on-line library of the IISS/IISW website;
An 87dB Single Exposure Dynamic Range CMOS Image Sensor with a 3.0µm Triple Conversion Gain Pixel
Back Side Illuminated High Dynamic Range 3.0μm Pixel Featuring Vertical p-n Junction Capacitance in A Deep Pinned Photodiode
A Proposal of PUF Utilizing Pixel Variations in the CMOS Image Sensor