A 4.0μm Stacked Digital Pixel Sensor Operating in A Dual Quantization Mode for High Dynamic Range

2021 September

Authors Kazuya Mori†, Naoto Yasuda†, Toshiyuki Isozaki†, Ken Miyauchi†, Isao Takayanagi†, Junichi Nakamura†, H. C. Chien‡, Ken Fu‡, SG.Wuu‡, Andrew Berkovich, Song Chen, Wei Gao and Chiao Liu
(†Brillnics Japan Inc., Japan ‡Brillnics Inc., Taiwan Facebook Reality Labs, Facebook Inc., USA)

Proceeding of the 2021 International Image Sensor Workshop, pp.308-311

the pixel has BSI photo diode circuit and ADC circuit. The bottom ADC operate with two different operation mode during exposure and after exposure.
During exposure, the photo charge is accumulated in a photo diode and its saturated change is designed to be overflown to the FD node w/o blooming during exposure.
If overflow charge at FD node reached to the reference level, its time code is toggled.
And a flag bit status is activated. If not, pixel memory is kept to be open to write and linear ADC take places after exposure and activated for accumulated photo signal.
Although, stored memory data is commonly used in different operating mode, the individual photo response characteristics of accumulated photo charge and overflow charge is normalized using flag bit data. As a result in prototype digital pixel sensor, High DR, High sensitivity, Low latency. Low power performance capability has been demonstrated w/ global shutter function.